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Rev. No. Approved date A July 17 2002
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
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Revision history
History Initial issue Remark (purpose) Preliminary
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
FEATURES * Single 3.0 V read, program, and erase Minimizes system level power requirements * Compatible with JEDEC-standard commands 2 Uses same software commands as E PROMs * Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) * Minimum 100,000 program/erase cycles * High performance 70 ns maximum access time * Sector erase architecture One 8K word, two 4K words, one 16K word, and fifteen 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase * Boot Code Sector Architecture T = Top sector B = Bottom sector TM * Embedded Erase Algorithms Automatically pre-programs and erases the chip or any sector TM * Embedded Program Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/ BY ) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Sector protection Hardware method disables any combination of sectors from program or erase operations * Sector Protection set function by Extended sector Protect command * Temporary sector unprotection Temporary sector unprotection via the RESET pin *: Embedded EraseTM and Embedded Program TM are trademarks of Advanced Micro Devices, Inc.
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GENERAL DESCRIPTION
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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The L29S800F/-B are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each. The L29S800F/-B are offered in a 48-pin TSOP(I) package, These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. The standard L29S800F/-B offer access times 70 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable ( CE ), write enable ( WE ), and output enable ( OE ) controls. The L29S800F/-B are pin and command set compatible with JEDEC standard E PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The L29S800F/-B are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The L29S800F/-B are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/ BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. LST's Flash technology combines years of EPROM and E PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The L29S800F/-B memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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FLEXIBLE SECTOR-ERASE ARCHITECTURE * One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes * Individual-sector, multiple-sector, or bulk-erase capability * Individual or multiple-sector protection is user definable. (x8) 16K byte 8K byte 8K byte 32K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte FFFFFH FBFFFH F9FFFH F7FFFH EFFFFH DFFFFH CFFFFH BFFFFH AFFFFH 9FFFFH 8FFFFH 7FFFFH 6FFFFH 5FFFFH 4FFFFH 3FFFFH 2FFFFH 1FFFFH 0FFFFH 00000H (x16) 7FFFFH 7DFFFH 7CFFFH 7BFFFH 77FFFH 6FFFFH 67FFFH 5FFFFH 57FFFH 4FFFFH 47FFFH 3FFFFH 37FFFH 2FFFFH 27FFFH 1FFFFH 17FFFH 0FFFFH 07FFFH 00000H 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 32K byte 8K byte 8K byte 16K byte (x8) FFFFFH EFFFFH DFFFFH CFFFFH BFFFFH AFFFFH 9FFFFH 8FFFFH 7FFFFH 6FFFFH 5FFFFH 4FFFFH 3FFFFH 2FFFFH 1FFFFH 0FFFFH 07FFFH 05FFFH 03FFFH 00000H (x16) 7FFFFH 77FFFH 6FFFFH 67FFFH 5FFFFH 57FFFH 4FFFFH 47FFFH 3FFFFH 37FFFH 2FFFFH 27FFFH 1FFFFH 17FFFH 0FFFFH 07FFFH 03FFFH 02FFFH 01FFFH 00000H
L29S800F Sector Architecture
L29S800F-B Sector Architecture
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BLOCK DIAGRAM
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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! PIN ASSIGNMENTS
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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Table 1 L29S800F/-B Pin Configuration Pin A-1, A0 to A18 DQ0 to DQ15 Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Unprotection Selects 8-bit or 16-bit mode No Internal Connection Device Ground Device Power Supply Function
CE OE WE
RY/ BY RESET BYTE N.C. VSS VCC
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LOGIC SYMBOL
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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Table 2 L29S800F/-B User Bus Operations ( BYTE = VIH) Operation Auto-Select Manufacturer Code (1) Auto-Select Device Code (1) Read (3) Standby Output Disable Write (Program/Erase) Enable Sector Protection (2), (4) Verify Sector Protection (2), (4) Temporary Sector Unprotection Reset (Hardware)/Standby
CE OE WE A0
L L L H L L L L X X L L L X H H VID L X X H X X H H H X H L L H A0 X X A0 L L X X
A1 L L A1 X X A1 H H X X
A6 L L A6 X X A6 L L X X
A9 VID VID A9 X X A9 VID VID X X
DQ0 to DQ15 Code Code DOUT HIGH-Z HIGH-Z DIN X Code X HIGH-Z
RESET H H H H H H H H VID L
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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Table 3 L29S800F/-B User Bus Operations ( BYTE = VIL) Operation Auto-Select Manufacturer Code (1) Auto-Select Device Code (1) Read (3) Standby Output Disable Write (Program/Erase) Enable Sector Protection (2), (4) Verify Sector Protection (2), (4) Temporary Sector Unprotection Reset (Hardware)/Standby Legend: L = VIL, H = VIH, X = VIL or VIH,
CE OE WE
L L L H L L L L X X L L L X H H VID L X X H X X H H H X H L
DQ15/ A-1 A0 L L A-1 X X A-1 L L X X L H A0 X X A0 L L X X
A1 L L A1 X X A1 H H X X
A6 L L A6 X X A6 L L X X
A9 DQ0 to DQ7 RESET VID VID A9 X X A9 VID VID X X Code Code DOUT HIGH-Z HIGH-Z DIN X Code X HIGH-Z H H H H H H H H VID L
= Pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See Table 7. 2. Refer to the section on Sector Protection. 3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 4. VCC = 3.3 V 10% 5. It is also used for the extended sector protection.
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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FUNCTIONAL DESCRIPTION Read Mode The L29S800F/-B have two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or change CE pin from "H" or "L" Standby Mode There are two ways to implement the standby mode on the L29S800F/-B devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition the current consumed is less than 5 A. The device can be read with standard access time (tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = "H". When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V ( CE = "H" or "L"). Under this condition the current is consumed is less than 5mA. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input. Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of L29S800F/-B data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To activate this mode, L29S800F/-B automatically switch themselves to low power mode when L29S800F/-B addresses remain stably during access fine of 150 ns. It is not necessary to control CE ,
WE , and OE on the mode. Under the mode, the current consumed is typically 1A (CMOS Level).
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and L29S800F/-B read-out the data for changed addresses. Output Disable With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the devices. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
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to VIH. All addresses are DON'T CARES except A0, A1, A6, and A-1. (See Table 4.1.) The manufacturer and device codes may also be read via the command register, for instances when theL29S800F/-B are erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 7. (Refer to Autoselect Command section.) Byte 0 (A0 = VIL) represents the manufacturer's code (LST = 04H) and (A0 = VIH) represents the device identifier code (L29S800F = DAH and 29S800F-B = 5BH for x8 mode; L29S800F = 22DAH and 29S800F-B = 225BH for x16 mode). These two bytes/words are given in the tables 4.1 and 4.2. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 4.1 and 4.2.)
Table 4 .1 L29S800F/-B Sector Protection Verify Autoselect Codes Type Manufacture's Code L29S800F Device Code 29S800F-B Sector Protection *1: A-1 is for Byte mode. *2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses. Byte Word Byte Word A12 to A18 X X X Sector Addresses A6 VIL VIL VIL VIL A1 VIL VIL VIL VIH A0 VIL VIH VIH VIL A-1
*1
Code (HEX) 04H DAH 22DAH 5BH 5BH 01H
*2
VIL VIL X VIL X VIL
Table 4 .2 Expanded Autoselect Code Table
Type
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacture's Code
L29S800F Device Code 29S800F-B Sector Protection
04H A-1/0 (B) DAH
0
0
0
0
0
0
0
0 1 1 0 0 0
0 1 1 1 1 0
0 0 0 0 0 0
0 1 1 1 1 0
0 1 1 1 1 0
1 0 0 0 0 0
0 1 1 1 1 0
0 0 0 1 1 1
A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 0 0 1 0
(W) 22DAH (B) 5BH (W) 225BH
A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
01H A-1/0
(B): Byte mode (W): Word mode
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Write
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
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Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE , whichever happens later; while data is latched on the rising edge of WE or CE , whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The L29S800F/-B feature hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 18). The sector protection feature is enabled using programming equipment at the user's site. The devices are shipped with all sectors unprotected. Alternatively, LST may program and protect sectors in the factory prior to shipping the device. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE , (suggest VID = 11.5 V), CE = VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. Tables 5 and 6 define the sector address for each of the nineteen (19) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See Figures 16 and 24 for sector protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the devices will read 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON'T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order addresses (A18, A17, A16, A15, A14, A13, and A12) are the desired sector address will produce a logical "1" at DQ0 for a protected sector. See Tables 4.1 and 4.2 for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the L29S800F/-B devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12 V). During this mode, formerly protected sectors can be programmed or erased by selecting
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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the sector addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again. See Figures 17 and 25.
RESET
Hardware Reset
The L29S800F/-B devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode 20 s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/ BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality. If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) cannot be used.
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Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
Table 5 Sector Address Tables (L29S800F) A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 A14 X X X X X X X X X X X X X X X 0 1 1 1 A13 X X X X X X X X X X X X X X X X 0 0 1 A12 X X X X X X X X X X X X X X X X 0 1 X Address Range (x8) 00000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to F7FFFH F8000H to F9FFFH FA000H to FBFFFH FC000H to FFFFFH
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Address Range (x16) 00000H to 07FFFH 08000H to 0FFFFH 10000H to 17FFFH 18000H to 1FFFFH 20000H to 27FFFH 28000H to 2FFFFH 30000H to 37FFFH 38000H to 3FFFFH 40000H to 47FFFH 48000H to 4FFFFH 50000H to 57FFFH 58000H to 5FFFFH 60000H to 67FFFH 68000H to 6FFFFH 70000H to 77FFFH 78000H to 7BFFFH 7C000H to 7CFFFH 7D000H to 7DFFFH 7E000H to 7FFFFH
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Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A18 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
Table 6 Sector Address Tables (29S800F-B) A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 1 X X X X X X X X X X X X X X X A13 0 1 1 X X X X X X X X X X X X X X X X A12 X 0 1 X X X X X X X X X X X X X X X X Address Range (x8) 00000H to 03FFFH 04000H to 05FFFH 06000H to 07FFFH 08000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to FFFFFH
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Address Range (x16) 00000H to 01FFFH 02000H to 02FFFH 03000H to 03FFFH 04000H to 07FFFH 08000H to 0FFFFH 10000H to 17FFFH 18000H to 1FFFFH 20000H to 27FFFH 28000H to 2FFFFH 30000H to 37FFFH 38000H to 3FFFFH 40000H to 47FFFH 48000H to 4FFFFH 50000H to 57FFFH 58000H to 5FFFFH 60000H to 67FFFH 68000H to 6FFFFH 70000H to 77FFFH 78000H to 7FFFFH
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Command Sequence Word Byte Word Read/Reset Byte Word Autoselect Byte Word Program Byte Word Chip Erase Byte Word Sector Erase Byte
Read/Reset Bus Write Cycles Req'd
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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Table 7 L29S800F/-B Standard Command Definitions Fourth Bus Sixth Bus Fifth Bus First Bus Second Bus Third Bus Read/Write Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data XXXH F0H 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH AAH AAH AAH AAH AAH -- 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H -- 55H 55H 55H 55H 55H -- 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH -- F0H 90H A0H 80H -- RA -- PA -- RD -- PD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1 3 3 4 6 6
555H 2AAH 555H AAH 55H 10H AAAH 555H AAAH 555H 2AAH AAH 55H SA 30H 80H AAAH 555H
Sector Erase Suspend Erase can be suspended during sector erase with Addr. ("H" or "L"). Data (B0H) Sector Erase Resume Erase can be resumed after suspend with Addr. ("H" or "L"). Data (30H) Notes: 1. Address bits A11 to A18 = X = "H" or "L" for all address commands except or Program Address (PA) and sector Address (SA) 2. Bus operations are defined in Tables 2 and 3. 3. RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of WE . 5. The system should generate the following address patterns: Word Mode: 555H or 2AAH to addresses A0 to A10 Byte Mode: AAAH or 555H to addresses A-1 and A0 to A10 6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
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Command Sequence Set to Fast Mode Fast *1 Program Reset from *1 Fast Mode Extended Sector *2 Protect Word Byte Word Byte Word Byte Word Byte
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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Table 8 L29S800F/-B Extended Command Definitions
Bus Write Cycles Req'd 3 First Bus Write Cycle Addr 555H AAAH XXXH XXXH XXXH XXXH XXXH Data AAH Second Bus Write Cycle Addr 2AAH 555H PA XXXH XXXH SPA Data 55H Third Bus Write Cycle Addr 555H AAAH -- Data 20H Fifth Bus Write Cycle Addr -- Data --
2
A0H
PD
--
--
--
2
90H
F0H*
3
--
--
--
--
4
60H
60H
SPA
40H
SPA
SD
SPA : Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector addresses. *1:This command is valid while Fast Mode. *2:This command is valid while RESET =VID. *3:This data "00H" is also acceptable.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
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Autoselect Command
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
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Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read cycle from address XX01H for x16(XX02H for x8) returns the device code (L29S800F = DAH and 29S800F-B = 5BH for x8 mode; L29S800F = 22DAH and 29S800F-B = 225BH for x16 mode). (See Tables 4.1 and 4.2.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address XX02H for x16 (XX04H for x8). Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector. The programming verification should be perform margin mode on the protected sector. (See Tables 2 and 3.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and also to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE , whichever happens later and the data is latched on the rising edge of CE or WE , whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 9, Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Figure 20 illustrates the Embedded Program operations.
TM
Algorithm using typical command strings and bus
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Chip Erase
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming) Figure 21 illustrates the Embedded Erase operations.
TM
Algorithm using typical command strings and bus
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE , while the command (Data=30H) is latched on the rising edge of WE . After time-out of 50 s from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 7. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 s otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 ms from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 s time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 18). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 50 s time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the devices return to the read mode. Data polling must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
TM
PRELIMINARY
A
Figure 21 illustrates the Embedded Erase operations. Erase Suspend
Algorithm using typical command strings and bus
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command resumes the erase operation. The addresses are DON'T CARES when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 20s to suspend the erase operation. When the devices have entered the erasesuspended mode, the RY/ BY output pin and the DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the RY/ BY output pin, Data polling of DQ7, or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
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Extended Command
(1) Fast Mode
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
L29S800F/-B has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to the Figure 27 Extended algorithm.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to the Figure 27 Extended algorithm.) (3) Extended Sector Protection In addition to normal sector protection, the L29S800F/-B has Extended Sector Protection as extended function. This function enable to protect sector by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60H) into the command register. Then, the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector to be protected (recommend to set VIL for the other addresses pins), and write extended sector protect command (60H). A sector is typically protected in 150 ms. To verify programming of the protection circuitry, the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40H). Following the command write, a logical "1" at device output DQ0 will produce for protected sector in the read operation. If the output data is logical "0", please repeat to write extended sector protect command (60H) again. To terminate the operation, it is necessary to set RESET pin to VIH.
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Write Operation Status
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
Table 9 Hardware Sequence Flags Status Embedded Program Algorithm Embedded Erase Algorithm In Progress Erase Suspended Mode Erase Suspend Read (Erase Suspended Sector) Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) DQ7
DQ7
DQ6 Toggle Toggle 1 Data Toggle (Note 1) Toggle Toggle Toggle
DQ5 DQ3 0 0 0 0 1 0
DQ2 1 Toggle Toggle Data 1 (Note 2) 1 N/A N/A
0 1 Data
DQ7 DQ7
Data Data 0 1 1 1 0 0 1 0
Embedded Program Algorithm Exceeded Time Limits Embedded Erase Algorithm Erase Suspended Mode Erase Suspend Program (Non-Erase Suspended Sector)
0
DQ7
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle. 2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. 3. DQ0 and DQ1 are reserve pins for future use. 4. DQ4 is LST internal use only.
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DQ7 Data Polling
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
The L29S800F/-B devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 22. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the L29S800F/-B data pins (DQ7) may change asynchronously while the output enable ( OE ) is asserted low. This means that the devices are driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See Table 9.) See Figure 9 for the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I The L29S800F/-B also feature the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read ( OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 ms and then stop toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 s and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. See Figure 10 for the Toggle Bit I timing specifications and diagrams.
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DQ5
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Tables 2 and 3. The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the DQ5 bit will indicate a "1." Please note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See Table 9: Hardware Sequence Flags.
DQ2
Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also Table 9 and Figure 18. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector.
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Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) (Note 1) Erase-Suspend Program
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
DQ7
DQ7
DQ6 Toggle Toggle 1 Toggle (Note 1)
DQ2 1 Toggle Toggle 1 (Note 2)
0 1
DQ7
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle. 2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
RY/ BY
Ready/Busy The L29S800F/-B provide a RY/ BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or erase operation. When the RY/ BY pin is low, the devices will not accept any additional program or erase commands. If the L29S800F/-B are placed in an Erase Suspend mode, the RY/ BY output will be high. During programming, the RY/ BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/ BY pin is driven low after the rising edge of the sixth WE pulse. The RY/ BY pin will indicate a busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing diagram. The RY/ BY pin is pulled high in standby mode. Since this is an open-drain output, RY/ BY pins can be tied together in parallel with a pull-up resistor to VCC.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the L29S800F/-B devices. When this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer to Figures 13, 14 and 15 for the timing diagram.
Data Protection
The L29S800F/-B are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. 24 071802
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Low VCC Write Inhibit
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 2.3 V. If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE , CE , or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle
CE and WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE . The internal state machine is automatically reset to the read mode on power-up.
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
ABSOLUTE MAXIMUM RATINGS Storage Temperature ..............................................................................................-55C to +125C Ambient Temperature with Power Applied ..............................................................-40C to +85C Voltage with respect to Ground All pins except A9, OE , RESET (Note 1) ...........-0.5 V to VCC+0.5 V VCC (Note 1) ...........................................................................................................-0.5 V to +5.5 V A9, OE , and RESET (Note 2) ............................................................................-0.5 V to +13.0 V Notes: 1. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitions, inputs may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on A9, OE and RESET pins are -0.5 V. During voltage transitions, A9,
OE and RESET pins may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE and RESET pins are +13.0 V which may positive overshoot to 14.0
V for periods of up to 20 ns. Voltage difference between input voltage and supply voltage (VIN - VCC) do not exceed 9 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
RECOMMENDED OPERATING RANGES Ambient Temperature (TA) ........................................................................................ -40C to +85C VCC Supply Voltages L29S800F-70/B....................................................................................................... +3.0 V to +3.6 V L29S800F-90/B /-12/B ........................................................................................... +2.7 V to +3.6 V Operating ranges define those limits between which the functionality of the devices are guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their LST representatives beforehand.
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MAXIMUM OVERSHOOT
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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DC CHARACTERISTICS Parameter Symbol ILI ILO ILIT
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
Parameter Description Input Leakage Current Output Leakage Current A9, OE , RESET Inputs Leakage Current
Test Conditions VIN = VSS to VCC, VCC = VCC Max.
VOUT = VSS to VCC, VCC = VCC Max.
Min. -1.0 -1.0 -- Byte Word Byte Word -- -- -- -- --
Max. +1.0 +1.0 35 22 25 12 15 35 5 5
Unit A A A mA mA mA A A A V V V V V V V
VCC = VCC Max. A9, OE , RESET = 12.5 V
ICC1
VCC Active Current (Note 1)
CE = VIL, OE = VIH, f=10 MHz CE = VIL, OE = VIH, f=5 MHz CE = VIL, OE = VIH
ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1 VOH2 VLKO
VCC Active Current (Note 2) VCC Current (Standby) VCC Current (Standby, Reset)
VCC = VCC Max., CE = VCC 0.3 V, RESET = VCC 0.3 V VCC = VCC Max., RESET = VSS 0.3 V
VCC = VCC Max., CE = VSS 0.3 V, VCC Current RESET = VCC 0.3 V (Automatic Sleep Mode) (Note 3) VIN = VCC 0.3 V or VSS 0.3 V Input Low Level Input High Level Voltage for Autoselect and Sector Protection (A9, OE RESET ) (Note 4) Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage -- -- -- IOL = 4.0 mA, VCC = VCC Min. IOH = -2.0 mA, VCC = VCC Min. IOH = -100 A --
-- -0.5 2.0 11.5
5 0.6 VCC+0.3 12.5 0.45
2.4 VCC-0.4 2.3
-- -- 2.5
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 10 MHz). 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. (VID - VCC) do not exceed 9 V.
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AC CHARACTERISTICS
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
* Read Only Operations Characteristics Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- -- Standard tRC tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, -- Min.
Description
Test Setup
-12 -90 -70 Unit (Note) (Note) (Note) 70 70 70 30 25 25 0 20 5 90 90 90 35 30 30 0 20 5 120 120 120 50 30 30 0 20 5 ns ns ns ns ns ns ns s ns
CE = VIL Max. OE = VIL
OE = VIL Max.
-- -- -- -- -- -- Max. Max. Max. Min. Max. Max.
CE or OE , Whichever Occurs First
RESET Pin Low to Read Mode
CE or BYTE Switching Low or High
Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (L29S800F/-B-70) 1 TTL gate and 100 pF (L29S800F/-B-90/-12) Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output:1.5 V
3.3V IN3064 or Equivalent
Device Under Test CL
2.7k
6.2k Diodes=IN3064 or Equivalent
Note:1.CL=30pF including jig capacitance (-70) 2.CL=100pF including jig capacitance(-90/-120) Figure 4 Test Condition
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Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX -- -- tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- -- -- -- -- Standard tWC tAS tAH tDS tDH tOES tOEH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVLHT tWPP tOESP tCSP tRB tRP tRH
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
* Write/Erase/Program Operations Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. 70 0 45 35 0 0 0 10 0 0 0 0 0 0 35 35 25 25 8 1 50 500 4 100 4 4 0 500 200 L29S800F/-B -70 -90 90 0 45 45 0 0 0 10 0 0 0 0 0 0 45 45 25 25 8 1 50 500 4 100 4 4 0 500 200 -12 120 0 50 50 0 0 0 10 0 0 0 0 0 0 50 50 30 30 8 1 50 500 4 100 4 4 0 500 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s sec s s s s ns ns ns Unit
Read Recover Time Before Write Read Recover Time Before Write
CE Setup Time
WE Setup Time
CE Hold Time
WE Hold Time Write Pulse Width
CE Pulse Width
Write Pulse Width High
CE Pulse Width High
Byte Programming Operation Sector Erase Operation (Note 1) VCC Setup Time Rise Time to VID (Note 2) Voltage Transition Time (Note 2) Write Pulse Width (Note 2)
OE Setup Time to WE Active (Note 2) CE Setup Time to WE Active (Note 2)
Recover Time From RY/ BY RESET Pulse Width RESET Hold Time Before Read
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(Continued) Parameter Symbols JEDEC -- -- -- -- Standard tFLQZ tFHQV tBUSY tEOE
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
Description BYTE Switching Low to Output High-Z BYTE Switching High to Output Active Program/Erase Valid to RY/ BY Delay
Delay Time from Embedded Output Enable
L29S800F/-B -70 Max. Min. Max. Max. 30 30 90 30 -90 35 35 90 35 -12 50 50 90 50
Unit ns ns ns ns
Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Protection operation.
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SWITCHING WAVEFORMS
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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Addresses
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
tRC Addresses Stable tACC
CE
tOE OE
tDF
tOEH
WE
tCE High-Z
Outputs
Output Valid
High-Z
Figure 5.1 AC waveforms for Read Operations
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
tRC Addresses tRH RESET tOH Outputs High-Z Output Valid tACC Addresses Stable
Figure 5.2 AC Waveforms for Hardware Reset/Read Operations
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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CE
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
The rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY
Figure 11 RY/BY Timing Diagram during Program/Erase Operations
WE
RESET tRP RY/BY tREADY
Figure 12 RESET/RY/BY Timing Diagram
tRB
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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! FLOW CHART
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
Start
RESET=VID (Note 1) Perform Erase or Program Operations
RESET=VIH
Temporary Sector Unprotection Completed (Note 2) Notes: 1.All protected sectors are unprotected. 2.All previously protected are protected once again.
Figure 25 Temporary Sector Unprotection Algorithm
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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!
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Min. Typ. 1 16 8 8.4 -- Max. 10 360 300 25 -- sec s s sec cycles Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead -- Unit -- -- -- -- 100,000 Comments
Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle
!
TSOP(I) PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ. 7.5 8 10 Max. 9.5 10 13 Unit pF pF pF
Note: Test condition TA=25, f=1.0MHz
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L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
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Part Number Information
L29S800F 8MEGABIT (1Mx8 /512Kx16) 3 VOLT CMOS FLASH MEMERY
PRELIMINARY
A
54
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